The present invention relates to a semiconductor device of a large scale integration (LSI) and, more specifically, relates to the improvement of a so-called masterslice semiconductor device fabricated from a large number of basic cells arranged along both rows and columns of a semiconductor substrate.
Masterslice semiconductor technology is proposed as a means for providing custom-tailored large scale integration (LSI) semiconductor circuits at a low cost and within a short turnaround time. That is, a large number of basic cells each including transistors and resistors, which are formed in a semiconductor chip in advance, are interconnected by the use of masks having wiring patterns necessary for realizing a functional circuit to meet each customer's specific requirements.
FIG. 1 is a plan view showing the conventional bulk pattern of a gate array formed by use of the masterslice technology. As illustrated in FIG.1, on a semiconductor substrate chip 100, the basic cells BC are arranged along the columns and constitute basic cell arrays BL.sub.1, BL.sub.2, .sup.... B.sub.n. Each of the basic cells BC is, in general, comprised of at least a pair of p-channel and n-channel MIS (Metal Insulator Semiconductor) transistors (to be simply referred to as p-channel and n-channel transistors, hereinafter).
The basic cell arrays are arranged with a specified space therebetween along the rows. At the periphery of the chip 100, there is a pad region, which is allotted for a plurality of pads, PD, used as the terminals to the external circuit, and an input/output (I/O) cell region, which is allotted for a plurality of I/O cells, IOC, each containing an input/output (I/O) circuit (not shown). As described later, each space between adjacent basic cell arrays is used for distributing the wiring lines interconnecting the basic cells in a basic cell array and/or the basic cells in different basic cell arrays.
FIG. 2 is an equivalent circuit diagram of an example of a conventional basic cell comprised of two pairs of p-channel and n-channel transistors. In FIG. 2, each pair of a p-channel transistor and an n-channel transistor, i.e. the first pair comprising a p-channel transistor QP.sub.1 and an n-channel transistor QN.sub.1, the second pair comprising a p-channel transistor QP.sub.2 and an n-channel transistor QN.sub.2, have a single common gate, and the p-channel transistors QP.sub.1 and QP.sub.2 have a single common source or drain, while the n-channel transistors QN.sub.1 and QN.sub.2 have a single common source or drain.
FIG. 3 is a plan view illustrating an exemplary bulk pattern of the basic cell embodying the circuit shown in FIG.2. The masterslice semiconductor device comprised of basic cells each having such a bulk pattern has been disclosed in U.S. Pat. No. 4,412,237 issued Oct. 25, 1983, for example.
In FIG. 3, like reference characters designate like or corresponding parts in FIG. 2, and further, reference numerals 1 and 2 designate a p-type region and an n-type region, respectively, both 3G.sub.1 and 3G.sub.2 represent polysilicon gate electrodes, and 4CP and 4CN denote a p-type contact region and an n-type contact region, respectively. The p-type region 1 is for constituting the sources and drains of the p-channel transistors QP.sub.1 and QP.sub.2, while the n-type region 2 is for constituting the sources and drains of the n-channel transistors QN.sub.1 and QN.sub.2. Each of the contact regions 4CP and 4CN provided with a relatively low resistivity is used as an electrode for keeping each portion of the semiconductor substrate at a respective potential.
In the masterslice semiconductor technology, an LSI circuit is comprised of a number of elementary circuits including a 2-input NAND gate, 2-input NOR gate and/or flip-flop circuit. Each of the elementary circuits is organized by using a single or a plurality of basic cells such as shown in FIGS. 2 and 3. The area occupied by the basic cells constituting each elementary circuit is referred to as a unit cell. In the prior art, each such unit cell is comprised of basic cells successively arranged in the same basic cell array. FIG. 4 is a conceptual diagram representing the prior art configuration of the unit cell UC (the hatched area) in a basic cell array BL. The basic cells in the unit cell UC are interconnected by use of a so-called double-layer aluminum metallization technology, wherein the aluminum wiring lines interconnecting the basic cells belonging to the unit cell are exclusively permitted to pass through, that is, over, the region occupied by the basic cells.
Interconnections among the unit cells are also accomplished by use of the double-layer aluminum metallization technology, however, the aluminum wiring lines for this purpose must be formed in the space between the adjacent basic cell arrays. This limitation is imposed by the performance of the CAD (Computer Aided Design) system employed for designing the layout of the circuit network of a masterslice semiconductor device.
These wiring lines formed in the space between adjacent basic arrays are assumed to be arranged on a virtual grid having a constant pitch. FIG. 5 is a plan view showing an exemplary layout of an aluminum wiring line interconnecting two adjacent basic cell arrays BL.sub.1 and BL.sub.2. In FIG.5, the wiring line consisting of the segments indicated by LA and LB are laid out on the virtual grid situated in the space between two adjacent basic arrays BL.sub.1 and B.sub.2. The virtual grid is, of course, not apparent in the actual pattern but only exists as a logical image in the process of CAD. If it is assumed that there are nine grid lines along the longitudinal direction of the basic cell arrays BL.sub.1 and BL.sub.2, nine wiring lines such as LA can be accommodated in the space. Such space is referred to as a wiring region of nine channels. The virtual grid lines in the transverse direction are similarly defined.
According to the double-layer aluminum metallization as described above, each segment LA extending along the longitudinal direction of the basic cell arrays is fabricated from the first wiring layer, while each segment LB extending perpendicularly to the longitudinal direction of the basic cell arrays is fabricated from the second wiring layer, each wiring layer is formed of aluminum, in general. The segments LA and LB are connected to other at each cross-over points marked with the doubled-circle NB, via a through-hole formed in the insulating layer therebetween. Thus, the interconnection between the basic cells in the two adjacent basic cell arrays is completed.
As mentioned before, in the prior art masterslice technology, the basic cells constituting a unit cell must be those belonging to the same basic cell array. That is, a unit cell must be one-dimensional in terms of the arrangement of the basic cells. This is mainly due to the performance of the present CAD systems employed for the network design of the masterslice semiconductor device. To manufacture a final masterslice semiconductor device within a required short turnaround time, it is necessary to minimize the design parameters which are defined in the CAD system. If a unit cell were defined to be two-dimensional in terms of the arrangement of the basic cells, the number of the parameters should be too large to finish the network design in a desired period. Therefore, each unit cell is formed in one basic cell array, and interconnections between adjacent basic cell arrays are conducted on a unit cell basis, and not on a basic cell basis.
As the result of the restriction that a unit cell must be one-dimensional in the sense mentioned above, both of the two kinds of the wiring lines, namely the first kind for interconnecting basic cells in a unit cell and the second kind for interconnection among unit cells, become long, and further the variety and the scale of the unit cell are limited by the number of the channels available in the space between adjacent basic cell arrays. As a wiring line becomes longer, the propagation delay of the signals in the circuit network of the masterslice semiconductor device increases because of the increase in the parasitic capacity of the wiring line. When such propagation delay becomes significant, the delay is usually compensated by providing a means such as a block-buffer circuit which has a high driving capability; however, a number of basic cells must be allotted for constituting the block-buffer circuit. For example, eleven of the basic cells, each having the configuration as shown in FIG. 2, are necessary for constituting one block-buffer circuit. Therefore, in a case wherein it is necessary to implement a number of block-buffer circuits, the basic cells available for constituting desired unit cells are decreased. As a result, the variety of circuits obtainable by use of the masterslice technology is also limited.
On the contrary, if it were possible to constitute a unit cell by extending beyond the space between the adjacent basic cell arrays, that is, if the unit cell were two-dimensional in terms of the arrangement of the basic cells, the problem of the propagation delay of the signals and other inconveniences which arise from the above-mentioned restriction in the prior art unit cell configuration could be eliminated, and the freedom in the circuit design of a masterslice semiconductor device could be substantially increased.